Design an exchange matching engine
Design the core matching engine for a single-venue equities exchange: 5,000 instruments, peak 2M orders/s, price-time priority, limit/market/IOC/FOK orders, and deterministic recovery after a crash.
Prep: weeks 6, 7, 8, 9, 12, 36
Design a market-data feed handler
Design a feed handler that consumes an exchange’s UDP multicast feed (A/B lines, ~10M messages/s at the open), builds full-depth order books for 20,000 instruments, and publishes normalized top-of-book to strategies in the same box with minimal latency.
Prep: weeks 10, 11, 16, 29, 30, 33, 46
Design an order gateway with pre-trade risk
Design the order-entry gateway for a broker: thousands of client FIX/binary sessions, pre-trade risk checks (credit, position, fat-finger, rate limits), routing to three exchanges, and a kill switch. Target p99 under 20 µs gateway-internal.
Prep: weeks 13, 14, 15, 17, 20, 24
Design market-data fan-out to 10,000 web clients
An exchange wants to stream real-time order book updates to 10,000 retail WebSocket clients and 50 institutional clients over TCP, without slowing the core. Design the distribution layer.
Prep: weeks 16, 19, 23, 24
Design a real-time position, PnL and risk service
Design a service that tracks positions and PnL for 300 trading strategies in real time from fills and market data, enforces post-trade limits (max loss, gross exposure), and can halt a strategy within 1 ms of a breach.
Prep: weeks 15, 45, 39
Design a tick-to-trade path for a market maker
A market maker quotes 500 instruments on one exchange. Design the box: from a market-data packet arriving to an updated quote leaving, with a target of 2 µs median and a tight p99.
Prep: weeks 21, 25, 30, 31, 33, 38, 39, 42
Design a backtesting platform
Design a backtesting platform for intraday strategies that replays a year of full-depth market data across 2,000 instruments, simulates exchange matching and latency, and returns results to researchers within minutes.
Prep: weeks 44, 46, 43
Design low-latency logging and audit
Trading components must log every order event for audit and debugging without adding more than 50 ns to the hot path. Design the logging and audit pipeline.
Prep: weeks 9, 19, 27